This invention relates a circuit arrangement for analog-to-digital conversion comprising an analog subtracter whose subtract input is coupled to the output of a digital-to-analog converter, an analog-to-digital converter connected to the output of the analog subtracter, and a control device and a device for error correction.
A circuit arrangement for analog-to-digital conversion is known, for example, from U.S. Pat. No. 4,618,850. An analog voltage, sampled by means of a sample-and-hold element, is applied to a first input of a subtracter. The output of the subtracter is connected to an analog-to-digital converter having a 4-bit resolution. The four-bit digital output value of the analog-to-digital converter is transferred to a first input of a digital adder. The output value of the adder is buffered in a sum register and is fed out via an output register. The output of the sum register is connected to the input of a digital-to-analog converter having a five-bit resolution. The output of the digital-to-analog converter is connected to a second input of the analog subtracter. The analog subtracter forms a difference voltage between the analog voltages applied to its first input and its second input.
Prior to analog-to-digital conversion a control device resets the sum register to zero. As a result of this, the output value of the digital-to-analog converter is zero so that the voltage applied to the first input of the analog subtracter passes this subtracter without being changed. The analog-to-digital converter quantizes this voltage and generates a corresponding digital value. This value is stored in the sum register and is applied to the digital-to-analog converter. The analog output voltage of the digital-to-analog converter deviates from the analog input voltage as a result of the coarse quantization and possible linearity errors of the analog-to-digital converter in the first conversion step. The analog subtracter forms the difference voltage, which generates a second digital word in a second conversion step. In the adder the first and the second digital words are combined to form a word having a length of five bits. The digital adder and the sum register form a circuit unit for error correction to provide compensation for quantization errors of the analog-to-digital converter. Thus, by means of an n-bit analog-to-digital converter and an n+1 bit digital-to-analog converter an accurate n+1 bit result is obtained in two conversion steps.